A Block Coprocessor for User Data Rate Improvements to GPRS Coding Scheme 4

A block coprocessor for user data rate improvements to GPRS coding scheme 4. It is advisable to refer to the publisher's version if you intend to cite from the work. A block coprocessor for user data rate improvements to GPRS coding scheme 4. Abstract The General Packet Radio Service (GPRS) has been developed to allow packet data to be transported efficiently over an existing circuit switched radio network, such as PCS or GSM. The main applications for GPRS are in transporting Internet Protocol (IP) datagram " s from web servers (for telemetry) or the user " s mobile Internet browsers to and from the Internet. Four GPRS baseband coding schemes are defined to offer a tradeoff in requested data rates versus propagation channel conditions. However, data rates in the order of >100kbits/second are only achievable if the simplest coding scheme is used (CS-4) which offers little error detection and correction (requiring excellent SNR) and the receiver hardware is capable of full duplex which is very expensive and not currently available in the consumer market. (BLER) performance is presented, particularly for coding scheme 4 (CS-4), however gains in other coding schemes are seen. For every GPRS radio block that is corrected by the EDC scheme, the block does not need to be retransmitted releasing bandwidth in the channel and improving the user " s application data rate. As GPRS requires intensive processing in the baseband, a viable hardware solution for a GPRS BLER co-processor is discussed that has been currently implemented in a Field Programmable Gate Array (FPGA) and presented in this paper. (BLER) performance is presented, particularly for coding scheme 4 (CS-4), however gains in other coding schemes are seen. For every GPRS radio block that is corrected by the EDC scheme, the block does not need to be retransmitted releasing bandwidth in the channel and 3 improving the user " s application data rate. As GPRS requires intensive processing in the baseband, a viable hardware solution for a GPRS BLER co-processor is discussed that has been currently implemented in a Field Programmable Gate Array (FPGA) and presented in this paper.